Programming and reading schemes of the memristor-based system:

We illustrate our detailed system overview in Fig. P1. In this figure, we present an m × n memristor array with peripheral circuits, where m and n represent the number of channels and segments, respectively. This design supports four operation modes including FORM, SET, PROCESS, and READ. The first three modes are used to electroform, set, and reset the memristors, respectively. The PROCESS mode is chosen to parallel process multichannel neural signals through RESET operations in this work. In the READ mode, 3-bit-resolution current sensing amplifier (CSA) serves as the readout circuit. Fig. P2 illustrates the programming scheme in the PROCESS mode. The activated BL and modules to process a certain segment of neural signals are color labeled, while those unused ones are drawn in gray. The parallelism is achieved in this mode by applying multichannel input signals to memristors in one column (i.e., segment) to modulate their conductances at the same time. The shift register controls and chooses to which memristor column the input signals are applied, and every time, there is only a WL turned on. Similarly, Fig. P3 shows the read scheme of the memristor array in the READ mode. When sensing and digitalizing the currents, CSAs clamp the SL voltages to 0.15 V, which is the read voltage, and then compare the currents with reference currents. Fig. P4 presents the FORM and SET schemes for the array. In these two modes, the memristor could be programmed in parallel or sequential fashion.

Figure P1. Memristor-based system overview. MUXs are used to select the operation modes, which include FORM, SET, PROCESS and READ. In the PROCESS mode, m-channel linearly transformed neural signals are parallel processed in the memristor array. In the READ mode, the currents are digitized through 3-bit-resolution CASs. Shift register is used to control the switching of WLs. In both PROCESS and READ modes, WLs are turned on sequentially, and only one WL opens at one time. BL: bit line; WL: word line; SL: source line; CAS: currentsensing amplifier; MUX: multiplexer; AND: And logic gate.

Figure P2. Array operation scheme in the PROCESS mode. Mode selection signal controls the MUXs to apply the m-channel input voltages on the source lines (SLs) of the memristor array and modulate the conductance of memristors in one column through RESET operation for parallel processing. All the bit lines (BLs) are connected to the ground. A shift register controls the word line (WL) to activate the memristor columns in the array one by one. The activated lines and modules are color-labeled, while those unused ones are drawn in grey.

Figure P3. Array operation scheme in the READ mode. To read memristor conductances, all bit lines (BLs) are connected to the ground and VWL are set to 4 V. The voltages of all the source lines (SLs) are clamped to 0.15 V by the CSAs. CSAs sense the currents of memristors in WL- selected column and compare them with reference currents, then output the digitized results. The activated lines and modules are color-labeled, while those unused ones are drawn in grey.

Figure P4. Array operation scheme in the FORM and SET modes. The shift register and VSL control and choose the memristors to form or set, for which VBL and VWL are applied through MUXs. The activated lines and modules are color-labeled, while those unused ones are drawn in grey.