2.2. MEMS Device Wafer Fabrication

The MOEMS devices were fabricated by the qualified IPMS process AME75, developed for electrostatic comb-driven micro scanning mirrors (Figure 11). They use 6” BSOI (bonded silicon-on-isolator) substrates with a 75 µm thick, highly p-doped SOI device layer, 1 µm buried oxide (BOX) layer, and 400 µm handling layer. Details of the MEMS process can be found, e.g., in [45]. For this work we have to point out the following specifics of the device wafer (DW) relevant for the MEMS WLVP:

Use of field isolation trenches (formed from DRIE-etched open trenches by thermal oxidation and refilling with polysilicon) to electrically isolate areas of different electrical potential within the same SOI layer needed to define the comb drives (Figure 10),

Use of AlSiCu metal lines for electrical signal transmission from the bond islands at outer chip frame to the inner comb drive actuator (no VIA (vertical interconnect access) exists),

Use of a thin protected aluminum layer as standard optical coating,

CMOS (complementary metal–oxide–semiconductor) compatibility of all inline processes due to restrictions caused by in-house CMOS processes for highly integrated micro mirror arrays [57].

Fabrication of device wafer: (a) MEMS process AM75; (b) backend integration of Au coating.

The standard Al coating is not possible to meet the high reflectance of R > 95% required for the NIR-FTS. Therefore, we used Au for reflection coating and a symmetric coating design for thermal compensation to guarantee a small static mirror deformation of ≤λ_min/10 after the WLVP process. Due to CMOS compatibility, in a backend process, identical Au coatings were deposited on the front and rear faces of the silicon mirrors using shadow masks for lateral patterning of the Au coatings.