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Fabrication of CMOS logic circuits

HY Hyeong Jin Yun
JL Jaehoon Lim
JR Jeongkyun Roh
DN Darren Chi Jin Neo
ML Matt Law
VK Victor I. Klimov
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NAND and NOR logic-gate devices (Fig. 5) were fabricated on top of a 300-nm SiO2/Si p++ wafer used as an underlying substrate but not a functional gate electrode. The input gate terminals used for applying VA and VB voltages were prepared from gold by thermal evaporation through a shadow mask. A 70-nm thick gate dielectric layer of Al2O3 was deposited by ALD using the same protocol as in the case of CMOS inverters (see previous section). The Au and In contacts defining, respectively, complementary p- and n-channel FETs were deposited by thermal evaporation through a shadow mask. A continuous 100-nm-thick film of NH4I-treated CQDs was prepared by spin-coating. The fabricated devices were annealed at 180 °C for 1 h and encapsulated into a layer of Al2O3 using ALD.

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