TLM device fabrication

90 nm Si/SiO₂ Substrate has been patterned using the EVG Aligner 620 photolithography with a chrome shadow mask. Substrate was prepatterned with independent back gate by etching 40 nm into Si/SiO₂ and depositing metal layer, followed by liftoff. An ALD layer of 8 nm Al₂O₃ or HfO₂ was deposited using Cambridge Savannah ALD Deposition Tool at 180 °C. ALD film quality was checked using non-contact mode AFM surface topography scanning. Few layer WSe₂ was obtained by mechanical exfoliation of commercially available Tungsten bulk crystal using the adhesive plastic film supplied by Ultron technology. Visual assessment of the optical contrast on TMD flakes on the PDMS resulted in the selection of WSe₂ flake with rectangular shape with uniform thickness. Selected flake was deterministically transferred using a custom-built transfer station at SAES lab on top of the ALD on trench gated region. Electron beam lithography was conducted with JEOL 6000FS to define the TLM pattern of source and drain electrodes using PMMA(Polymethyl methacrylate) as mask. followed by developed in IPA and MIBK (3:1) developer solution at room temperature. The metals (Pt/Au, Pd/Au) were deposited by E-beam metal evaporation (Lesker 3) at a rate of 2 Armstrong per second at a pressure of 10^–6 torr to ensure the uniformity of the electrode pads. Acetone was used to do liftoff to obtain the final TLM FET structure with a defined channel length of 400 nm, 800 nm and 1.8 µm. The approximate thickness of WSe₂ flakes used in this study are 3 ~ 5 atomic layer as verified by tapping mode atomic force microscopy (AFM) and Raman Spectroscopy. Stepped e-beam evaporation process, for instance, included several steps of 10 nm Pt depositions at a rate of 2 Å/s. After each 10 nm of deposition, the evaporation was stopped for an hour to allow the material to cool and return to room temperature.