Materials and characterization

The fabrication of ZnON layers involved the use of direct current (DC) reactive sputtering using a zinc (Zn) metal target, onto p ⁺⁺ Si/SiO₂ (SiO₂: 100 nm thick) substrates. The DC power was 100 W and the process pressure was kept at 5 mTorr without intentional heating of the substrates. A mixture of Ar/O₂/N₂ gas was used to generate the plasma, and the nitrogen gas flow rate (N₂/(N₂ + O₂)) was varied from 94.4 to 98.5%. For both thin film analyses and TFT fabrication, the ZnON layer thickness was maintained between 30~35 nm. To fabricate the devices, the active islands were patterned using shadow masks. To form the source-drain electrodes, a 100 nm-thick indium tin oxide (ITO) film was sputter deposited every time, using shadow masks as well. The resulting channel width and length of the devices are 800 and 200 µm, respectively. The electrical properties of the TFTs were evaluated using a HP4155A semiconductor parameter analyzer in a vacuum ambient in order to exclude environmental effects such as moisture permeation into ZnON. For the NBIS tests, the gate voltage (V_G) was maintained at −20 V, and the drain voltage (V_D) was kept at +10.1 V.