PEDOT:PSS (Clevios PH1000) was acquired from Heraeus. d-sorbitol (≥99.5%; BioUltra), chitosan (low molecular weight), (3-glycidyloxypropyl)trimethoxysilane (GOPS), 4-dodecyl benzene sulfonic acid (DBSA), 3-(trimethoxysilyl)propyl methacrylate (A-174 silane), and Micro 90 concentrated cleaning solution were purchased from Sigma-Aldrich. The 495 PMMA A4 (polymethyl methacrylate) resist was purchased from MicroChem. AZnLOF2020 (negative photoresist), AZ9260 (positive photoresist), AZ 400 K, and AZ 726 MIF (metal ion free) developers were acquired from MicroChemicals, Merck.

Cleaned 100-mm quartz wafers (thickness of 1 mm) were coated with a 2-μm-thick parylene layer, which provided a conformable substrate. We patterned the Au electrodes and interconnects via photolithography and lift-off processes. AZnLOF2020 was spin-coated (3000 rpm), baked on a proximity hot plate at 110°C for 90 s, exposed using a Suss MA6 Mask Aligner, and developed with AZ 726 MIF developer. Ti (10 nm) and Au (100 nm) layers were deposited with an e-beam metal evaporator (CHA Mark 50). Lift-off was performed by immersing the substrates in a bath with a 1165 stripper. An additional 2-μm parylene layer was coated on the samples to electrically isolate the Au electrodes. The adhesion of the second parylene layer was improved by using 3-(trimethoxysilyl)propyl methacrylate (A-174 silane) during coating. We spin-coated a dilution of micro 90 (8% in DI water) to form an antiadhesive layer. A sacrificial third parylene layer (2 μm) was deposited on top. We etched the areas that corresponded to transistor channels and contact pads via successive photolithography and plasma etching steps. AZ9260 was spin-coated (5000 rpm), baked at 115°C for 90 s, exposed using a Suss MA6 Mask Aligner, and developed with AZ400K developer (1:4 with DI water). The patterned areas were etched with a plasma reactive ion etching process [Oxford Plasmalab 80; 180 W, 50-sccm (standard cubic centimeters per minute) O2, and 2-sccm SF6]. A ~200-nm PEDOT:PSS (1% GOPS) and a ~700-nm chitosan (without any additional salt) layer were spin-coated successively to form the ion membrane interface that covers the gate electrode. To pattern the ion membrane, we used, in a similar manner to previous steps, photolithography and plasma etching after depositing a thin, protective PMMA layer (~200 nm) (37). Rinsing with acetone removed the photoresist and PMMA residues, leaving the ion membrane layers intact. Last, to realize the transistor channels, we spin-coated a mixture of PEDOT:PSS with d-sorbitol [40% d-sorbitol, 1% GOPS (as a cross-linker), and 0.1% DBSA (to improve film processing and wettability)] and patterned it by peeling off the third parylene layer (fig. S1). Unless otherwise stated, all films were deposited at 3000 rpm, resulting in approximately 2-μm-thick films. Care was taken to ensure complete coverage of metal pads by the conducting polymer to minimize parasitic capacitances. For deionized channel experiments, PEDOT:PSS films with the cross-linker (GOPS) were repetitively soaked in DI water baths five times, followed by deposition (spin coating at 1000 rpm) of 100% (w/v) sorbitol in DI water. To reintroduce ions into these devices, the DI water was replaced by a salt solution [phosphate buffered saline (PBS), NaCl, KCl, CaCl2, or MgCl2].

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