Triple-layer porous graphene on silicon/silicon nitride frames for interfacial polymerization

Freestanding triple layers of the porous graphene were prepared by subsequent transfer of three single porous graphene layers (2-nm W) to a silicon/silicon nitride (Si/SiNx) frame with an array of multiple 4-μm-wide openings. Si/SiNx chips were used, as PCTE is not compatible with chemicals such as toluene and EDA. Manufacturing of Si/SiNx and graphene transfer were performed following Celebi, Buchheim et al. (4). Briefly, silicon wafers coated with 150-nm-thick SiNx were purchased from Si-Mat Wafer Inc. Photolithography and reactive ion etching allowed the formation of defined pattern on the front and back sides of the wafer so that by subsequent KOH etching, freestanding SiNx membranes were obtained, having an 8 × 8 array of 4-μm-wide holes. The porous graphene was transferred by spin-coating PMMA and subsequently etching Cu using 0.5 M ammonium persulfate. By repeating this procedure three times, three-layer porous graphene was obtained. The PMMA/graphene was rinsed in DI water for 30 min before the next layer or the final substrate fished the graphene stack. The PMMA was removed by thermal annealing under H2 and Ar as carrier gas (atmospheric pressure, 9:1). The overall porosity of the triple-layer porous graphene was <0.1%. Triple-layer porous graphene is mechanically resilient enough to allow the postpolymerization thermal baking and subsequent handling of the membranes.

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