The vdWhs were prepared using CVD Gr from Graphenea on highly doped Si (with a thermally grown 285-nm-thick SiO2 layer). The Gr was patterned by photolithography and oxygen plasma etching and cleaned afterward by Ar/H2 annealing at 400°C for 90 min. The TI flakes (single crystals grown from a melt using a high vertical Bridgeman method, bought from Miracrys) were exfoliated by conventional scotch tape technique and dry-transferred on top of Gr. Next, appropriate 50- to 120-nm-thick BS or BSTS flakes located on Gr were identified by an optical microscope for device fabrication. The contacts were patterned on Gr (and TI flakes, in the case of vertical devices) by electron beam lithography. Finally, we used electron beam evaporation to deposit 1 nm of Ti, followed by in situ oxidation in a pure oxygen atmosphere for 2 hours to form a TiO2 tunneling barrier layer. Without exposing the device to ambient atmosphere, in the same chamber, we deposited 60 nm of Co, after which the devices were finalized by liftoff in warm acetone at 65°C. In the final devices, the Co/TiO2 contacts on Gr act as the source and drain for spin-polarized electrons, the Gr-TI heterostructure region serves as the channel, and the n++ Si/SiO2 is used as a back gate.

The FM tunnel contact resistances (Rc), measured in three-terminal configuration, were around 1 kΩ. Raman spectra measured on BS, BSTS, Gr, and Gr-TI heterostructures show good quality of the materials and their heterostructures (fig. S4). The field-effect mobility of the Gr channel in proximity with TIs was 630 to 1500 cm2 V−1 s−1. The observation of WAL in BS and BSTS and Shubnikov–de Haas (SdH) oscillations in BSTS shows the existence of a large spin-orbit interaction and 2D surface state conduction in the TI materials (21). The vertical transport properties of Gr-TI show tunneling behavior with an interface resistance of around 15 to 30 kΩ at zero-bias conditions (see fig. S3C).

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